1. Field of the Invention
The present invention pertains to electrically programmable non-volatile memories. It pertains, more especially, to electrically programmable non-volatile memories such as, for example, EPROM or EEPROM memories which set up a surge in the programming voltage.
Generally, in memories of the EPROM or EEPROM type, each data storage element or memory cell consists of a floating gate MOS transistor. A floating-gate MOS transistor may have two states. For an N-channel MOS transistor, in a first state, no charge is trapped at the floating gate. There may be a conduction channel between the source and the drain. The transistor is then conductive and behaves like a closed switch. In a second state, electrons have been trapped at the floating gate. They prevent the creation of a conduction channel in the substrate between the source and the drain. In this case, the transistor is off and behaves like an open switch. To program a floating-gate MOS transistor of the type described above, voltages higher than the normal operating voltage should be applied to the control gate and one of the electrodes in such a way that the floating gate can absorb and retain a charge of electrons. Furthermore, to read a memory thus programmed, a specific read voltage must be applied to the control gate. This read voltage is used to ascertain that the transistor is on or off.
In order to make it possible to apply the voltages needed to program or read a memory cell, consisting of a floating-gate MOS transistor, the said floating-gate MOS transistor is generally connected in the way shown in FIG. 1. Thus, one of the main electrodes of the floating-gate MOS transistor 1, namely the source 2 in the embodiment shown, is connected to the voltage V.sub.SS, representing the ground, while the other electrode or drain 3 is connected by a bit line (not shown) and a MOS transistor forming a switch 8 to a column address decoder 7. The control gate 5 of the MOS transistor 1 is connected by another connection, known as a word line (not shown) to a line address decoder 6. The bit lines and the word lines ae arranged in rows and columns to determine a matrix including the memory, cell formed by the floating-gate MOS transistor 1 known to one of ordinary skill in the art. In fact, the column address decoder 7 is connected to the gate of the transistor 8, which has its source connected to the drain 3 of the transistor 1 while its drain is connected to the write circuit E and to a read circuit, symbolized by the block L, respectively.
The write circuit E is made so that the programming voltage, namely the voltage V.sub.PP is applied at the node N when the memory cell 1 has to be programmed, i.e. when it has to record a datum corresponding to "1". On the contrary, if the memory cell 1 does not have to be programmed, the voltage at the node N during the write operation should remain at "0". As shown in FIG. 1, the write circuit is generally formed by a load line comprising a depleted MOS transistor 11, with one of its electrodes connected to the voltage V.sub.PP which constitutes the programming voltage, and its other electrode connected to one of the electrodes of an enhancement type MOS transistor 12. The other electrode of the transistor 12 is connected to the node N. The two gates of the transistors 11 and 12 are connected in common to a programming control circuit consisting of a NOR gate 13 powered by the voltage V.sub.PP. This NOR gate 13 receives, respectively, at its two inputs a signal D corresponding to the reversed datum to be programmed and a signal PGM corresponding to the reversed programming control signal. Consequently, with the above circuit, when the floating-gate MOS transistor 1 is programmed at the logic level "1", a current variation is observed in the supply of the programming voltage V.sub.PP.
In applications using electrically programmable non-volatile memories of the type described above, the memory cells are rarely programmed one by one. In fact, they are most often programmed in the form of a word, i.e. 8 memory cells for example, are programmed in parallel for a word with 8 binary positions or bits. Consequently, a current surge corresponding to 8 memory cells is observed in the supply of the programming voltage V.sub.PP . Now the current surge in the supply of a programming voltage V.sub.PP for a memory cell is generally about 1 to 2 milliamperes. Consequently, when all 8 memory cells are programmed at "1" for example, the current surge in the supply of the programming voltage V.sub.PP can rise up to a value ranging between 8 milliamperes and 16 milliamperes. Now, when there is a change from the programming or write mode to the read mode, the write circuits are de-activated on all 8 memory cells at the same time. This causes a sudden drop in consumption since the programming current I.sub.pp then goes from 16 milliamperes to 0 milliamperes. This variation in the programming current I.sub.PP may then cause a voltage peak in the supply of the programming voltage V.sub.PP. This peak can reach a value .DELTA.V.sub.PP of 7 volts. Now, this peak is very dangerous for all the circuits. For the transistors included in the circuits are designed to hold a maximum voltage defined by the technology used. This maximum voltage is 25 volts for 4-micron technology and 16 volts for 2-micron technology. There is therefore the danger that the variations in the programming voltage V.sub.pp which in fact is the highest voltage of the circuit, will destroy the circuit if the safeguards planned are exceeded and will consequently make the circuit unusable.
2. Brief Summary of the Present Invention
An object of the present invention is, therefore, to remove these disadvantages.
Consequently, an object of the present invention is an electrically programmable non-volatile memory comprising a matrix of memory cells accessible by rows and columns, with write and read circuits that apply potentials, representing the programmed datum or representing the read command, to the rows and columns, and means that handle the interconnection of the write and read circuits with the memory cells, a memory wherein N memory cells are programmed simultaneously (with N greater than 1) each memory cell making a current surge when it is programmed at "1", a memory further comprising first means to deactivate, one by one, the read circuits corresponding to the N memory cells during a change-over from a programming mode to a read mode, and second means to short-circuit the first means at the change-over to the programming mode.
According to a preferred embodiment, the first means comprise a shift register with one input, receiving the read/write control signal, and with N-1 outputs, the input and the N-1 outputs being respectively sent to N write circuits, the shift register being controlled by clock signals which switch over the outputs one by one. Furthermore, the second means to short-circuit the first means at the change-over to the programming mode comprise a combinative logic circuit activated by the read/write control signal and by the programming control signal generated at the end of the read operation, the combinative logic circuit being connected between the shift register and the write circuit s. The programming control signal is generated with the read/write control signal by means of a signal-separating circuit activated by the control signal of the Nth write circuit. Furthermore, the shift circuit receives a level resetting signal when it is turned on.